import chisel3._
import chisel3.util._
class Bram (addrWidth:Int) extends Module{
  val io = IO(new Bundle{
    val addr = Input(UInt(addrWidth.W))
    val writeEnable = Input(UInt(4.W))
    val rdata = Output(UInt(32.W))
    val wdata = Input(UInt(32.W))
  })
  val mem = Mem(1<<(addrWidth-2), Vec(4, UInt(8.W)))
  val memAddr = io.addr(addrWidth-1,2)
  val memOut = RegInit(VecInit(Seq.fill(4){0.U(32.W)}))

  io.rdata := Cat(memOut(3),memOut(2),memOut(1),memOut(0))
  for(i <- 0 until 4){
    memOut(i) <= mem(i)(memAddr)
    when(io.writeEnable(i)){
      mem(i)(memAddr) := io.wdata(i * 4 + 3,i * 4)
    }
  }
}
object BramGen {
  def main(args: Array[String]): Unit = {
    println("Generating hardware")
    chisel3.Driver.execute(Array("--target-dir", "generated"), () => new Bram(5))
  }
}